I. Field of Invention
The present invention relates generally to systems and methods for designing and manufacturing an integrated circuit. More particularly, the present invention relates to a method and apparatus for determining the performance of an integrated circuit that includes at least one of a plurality of deep-well trench dynamic random-access memory (DRAM) cells.
II. Description of the Related Art
Since modern integrated circuits frequently comprise more than one million transistors, systems and methods for designing complex integrated circuits are essential parts of the process of designing and manufacturing integrated circuits. Without such systems and methods, the design and manufacture of an integrated circuit would be prohibitively expensive.
To design an integrated circuit, a circuit diagram is first produced based on a functional description and specification of the integrated circuit. Generally, the properties of the circuit diagram are calculated with the assistance of a circuit simulator. If the circuit simulator determines that the circuit diagram does not satisfy the functional description and specification, modifications of the circuit diagram are made, and the properties of the modified circuit diagram are again calculated with the circuit simulator. The circuit diagram is modified and simulated until the properties of the circuit diagram satisfy the functional description and specification. With an acceptable circuit diagram, the production of a circuit layout based on the circuit diagram occurs. Using the circuit layout, masks are produced, which are ultimately used to manufacture or fabricate the integrated circuit.
In accordance with conventional approaches, the properties (e.g., relevant electrical circuit quantities corresponding to the functional description and specification) of an electronic device contained within an integrated circuit are calculated in the circuit simulator with the assistance of a model for the electronic device. For example, a transistor model provides relevant electrical circuit parameters for the terminal nodes of the transistor (e.g., source, drain, gate, and substrate) within an integrated circuit. The quality of the transistor model determines how well the properties that are calculated by the circuit simulator match the actual performance of the integrated circuit that is subsequently fabricated.
Numerous circuit simulators (also referred to as circuit emulation programs) exist including, for example, SPICE, ELDO, SMASH, SABER, VERILOG™, and VHDL. Developed at the University of California at Berkeley, SPICE (simulation program with emphasis on circuit emulation) is an integrated circuit emulation program, which emulates the performance of individual circuit elements (e.g., transistors). SPICE may be used to emulate the performance of one or more transistors in the circuit. SPICE programs are commercially available from a number of vendors (e.g., HSPICE, PSPICE). VERILOG™ or VHDL are hardware description languages, which may be used to describe integrated circuit design at a logic level. VERILOG-XL™ produced by Cadence Design Systems, Inc., of San Jose, Calif., is a software program that emulates the performance of a circuit described using the VERILOG™ hardware description language. The VERILOG-XL™ program may perform a number of functions. One function, for example, may be to calculate propagation delays generated by successive gates. The VERILOG-XL™ program may calculate such propagation delays and use delay information to calculate overall propagation delays for a particular cell or group of cells. Similarly, the simulation programs mentioned herein may simulate cell speed and noise.
In a circuit simulator, such as SPICE or VERILOG™, each electronic device contained within the integrated circuit is represented by a model. Such a model must be able to represent both static (i.e., slow) and dynamic (i.e., rapid) changes that affect the integrated circuit. The design of many DRAMS has to date not been able to benefit from accurate circuit simulation before fabrication because no accurate model for a deep-trench DRAM cell exists. One particularly difficult problem for such a model is representation of noise (e.g., crosstalk between adjacent devices).
The deep-trench DRAM cell is a logic device that, among other things, provides sufficient cell capacitance utilizing conventional insulator materials. Further, the deep-trench DRAM cell provides a smaller die size and softer error rates for a given geometry, when compared to other related devices. Consequently, the deep-trench DRAM cell permits easier integration with other devices in an integrated circuit environment. With smaller die sizes, the deep-trench DRAM cell also permits a design with a higher cell density, when compared to other related devices.